Forum Discussion
SKon1
Occasional Contributor
6 years agoHi sstrell,
I thought about it - but this also won't work.
I'll explain again what I want to do:
I want to connect component A (master) to component B (slave) which is inside QSYS and export the same bus outside of QSYS to component C (also slave).
Component C is written in RTL and does some monitoring on the address space of the Avalon Bus. It's completely passive and doesn't return any data to component A.
The problem with your suggested approach is that QSYS doesn't allow 2 Avalon MM slaves to share overlapping address spaces.