Hi, I would like to connect the Custom PHY Megafunction to my QSYS system. Well, [rant]OK, really: first I got to get this off my chest: I think it is just so ridiculous, that Altera did not make the Custom PHY QSYS compliant by themselves - it's just a massive waste of everyone's time, come on![/rant] I am using the pipeline bridge to make myself a nice conduit signal outside of QSYS I am using word adressing I set the address width of the pipeline bridge to 9, which corresponds to the Address width of the Custom PHY Symbol width??? What's that? I hook the signals together The bus stalls (or at least that's what I think it does, because I can't find my system ID in NIOS when I do this) So: What am I doing wrong (technically I mean, not by relying on Altera in the first place). I would attach pictures of my design, but the uploader doesn't work. Cheers, Peter

Hi Peter, I agree on your rant :) Which version of Quartus are you using, and which Custom PHY part are you trying to use? If you open an existing transceiver example ... http://www.altera.com/support/examples/on-chip-debugging/on-chip-debugging.html and then select the PHY in Qsys, you can right-click and find where the _hw.tcl source for the component is located. If you find your PHY in an example, your first question will be "Hang on, how is this PHY in Qsys, but I cannot see it in the IP Catalog!!!???". The answer is that for some reason Altera has set an attribute in _hw.tcl so that the component is hidden. You have to edit the _hw.tcl file and change set_module_property INTERNAL true to set_module_property INTERNAL false and then start the NIOS II IDE shell (Cygwin), change directory to Altera's .ipx file location and re-run ip-make-ipx to rebuild the IP Catalog. Yes, this is a complete PITA ... but at this point you will see the PHY listed in the IP Catalog. The main reason that the PHYs are not listed is probably that they are still buggy, so as they say "Your mileage may vary" :) Cheers, Dave

That was quick :) I am using Quartus 13.1 update 4 and I am designing for the Cyclone V... Thank you for the reply, I am going to try this out right now... and tell you how it went. But for the record: I am still kind of puzzled why my original solution does not work... Cheers, Peter

I was being too quick: Where do I find those files. Is the idea, that I have to do this for every project, or once for my Quartus installation?

--- Quote Start --- Where do I find those files. --- Quote End --- I already told you :) Download the Transceiver Toolkit examples from the link I referred to above (they were designed with 13.0sp1, but should open ok in 13.1). Open one of the existing Cyclone V projects and look at the path to the PHY. That will show you where in the Quartus installation the components are located. --- Quote Start --- Is the idea, that I have to do this for every project, or once for my Quartus installation? --- Quote End --- Just for your Quartus installation. Basically you are making the components visible to all projects. As for what is wrong with what you did above? My answer would be that you did not simulate using the Verification IP - that would answer any questions you have about the interface working correctly :) Cheers, Dave

Hi Dave, --- Quote Start --- I already told you --- Quote End --- Sorry, for not thinking for myself! It was only after I had posted, that I just saw you said I should right-click on the component in QSYS. The IP root folder was located in altera_install_dir/ip/altera on my machine. Many thanks, Dave!!!! Now the beast shows up in QSYS! --- Quote Start --- As for what is wrong with what you did above? My answer would be that you did not simulate using the Verification IP - that would answer any questions you have about the interface working correctly --- Quote End --- That is indeed true ;) Cheers, Peter

Export Avalon Bus for Custom PHY | Altera Community

15 Replies

Altera_Forum
Honored Contributor
11 years ago
If you change an _hw.tcl file, you *ALSO* have to re-run ip-make-ipx in the base directory containing the .ipx file. Eg., on the machine I am on I have an old web version ...

C:\software\altera\12.1sp1_free\ip\altera\altera_components.ipx

You need to start a NIOS II IDE shell (cygwin console), change to this directory, run ip-make-ipx, and then rename the generated components.ipx file.

I think that should do the trick ... at least it does for the Qsys stuff ... not sure about SOPC Builder _hw.tcl files though.

Cheers,
Dave

Altera_Forum

Honored Contributor

11 years ago

--- Quote Start ---

If you change an _hw.tcl file, you *ALSO* have to re-run ip-make-ipx in the base directory containing the .ipx file. Eg., on the machine I am on I have an old web version ...


C:\software\altera\12.1sp1_free\ip\altera\altera_components.ipx

You need to start a NIOS II IDE shell (cygwin console), change to this directory, run ip-make-ipx, and then rename the generated components.ipx file.

I think that should do the trick ... at least it does for the Qsys stuff ... not sure about SOPC Builder _hw.tcl files though.

Cheers,

Dave

--- Quote End ---

I did remake the components.ipx, regenerate my system, and remade the bsp. No luck so far. I also attempted to make my own custom bridge component and am trying to make that show up in system.h. No luck so far. The annoying thing is I have a bunch of custom components that come out fine, just haven't found the magic property yet.

I did find this reference though which has some of the properties, but not all. http://www.altera.com/literature/hb/qts/qsys_tcl.pdf

Here is what was in the _hw.tcl file for altera_avalon_mm_bridge


set_module_property DESCRIPTION "Inserts a register stage in the Avalon-MM command and response paths. Accepts commands on its Avalon-MM slave port and propagates them to its Avalon-MM master port."
set_module_property NAME altera_avalon_mm_bridge
set_module_property VERSION 13.1
set_module_property HIDE_FROM_SOPC true
set_module_property GROUP "Bridges and Adapters/Memory Mapped"
set_module_property AUTHOR "Altera Corporation"
set_module_property DISPLAY_NAME "Avalon-MM Pipeline Bridge"
set_module_property AUTHOR "Altera Corporation"
set_module_property TOP_LEVEL_HDL_FILE altera_avalon_mm_bridge.v
set_module_property TOP_LEVEL_HDL_MODULE altera_avalon_mm_bridge
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ELABORATION_CALLBACK elaborate
set_module_property ANALYZE_HDL FALSE
set_module_property SIMULATION_MODEL_IN_VHDL true
set_module_property HIDE_FROM_SOPC true
set_module_property DATASHEET_URL http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf

And here is what I changed it to:


set_module_property DESCRIPTION "Inserts a register stage in the Avalon-MM command and response paths. Accepts commands on its Avalon-MM slave port and propagates them to its Avalon-MM master port."
set_module_property NAME altera_avalon_mm_bridge
set_module_property VERSION 13.1
set_module_property HIDE_FROM_SOPC false
set_module_property GROUP "Bridges and Adapters/Memory Mapped"
set_module_property AUTHOR "Altera Corporation"
set_module_property DISPLAY_NAME "Avalon-MM Pipeline Bridge"
set_module_property AUTHOR "Altera Corporation"
set_module_property TOP_LEVEL_HDL_FILE altera_avalon_mm_bridge.v
set_module_property TOP_LEVEL_HDL_MODULE altera_avalon_mm_bridge
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ELABORATION_CALLBACK elaborate
set_module_property ANALYZE_HDL FALSE
set_module_property SIMULATION_MODEL_IN_VHDL true
set_module_property HIDE_FROM_SOPC false
set_module_property DATASHEET_URL http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf
set_module_property INTERNAL false

Altera_Forum
Honored Contributor
11 years ago
Oh there was also a part in the actual interface description which I didn't see in other modules.

set_interface_property s0 printableDevice false

I couldn't find any info on this property, but I tried removing this too and so far no luck.

It is possible that my system isn't picking up the new components.ipx file properly, haven't been able to confirm that yet.
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---

It is possible that my system isn't picking up the new components.ipx file properly, haven't been able to confirm that yet.
--- Quote End ---

Hit F5 to reload the components files, or exit Qsys and restart.

You could add a text message to the _hw.tcl file you are editing too, and then look for that message in the "Generate" console, eg.,

send_message info " *** INSERT MESSAGE HERE *** "

Cheers,
Dave
Altera_Forum
Honored Contributor
11 years ago
Ok so I've gotten around my issue finally. I created a custom addressable bridge component by copying the altera bridge and making some _hw.tcl changes.

The key thing is removing the
set_interface_property s0 bridgesToMaster m0
property in the avalon interface description.

This changes
<isBridge>true</isBridge>
to
<isBridge>false</isBridge>
which makes it show up in the system.h file. Obviously I didn't want all bridges to appear so that's why I made a custom bridge.

Hope this helps anyone that stumbles across this later.

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Export Avalon Bus for Custom PHY

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