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Altera_Forum
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14 years ago

Experienced Verilog coder has 2 Quartus-related VHDL questions..

Hi - after years of Verilog I'm coming up on VHDL. It's interesting. Two things I can't figure out, and since in both cases it's Quartus (not Modelsim) that's objecting, I thought i would ask here....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi Dave - the function approach worked out nicely as I had noted.

re ifdefs - just trying to get my general "tools" in order. So far, I used the generate to include/exclude parts of a testbench (printing different things for different runs).

I'll look at the references you mention - thanks!

/j