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Altera_Forum
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14 years ago

Experienced Verilog coder has 2 Quartus-related VHDL questions..

Hi - after years of Verilog I'm coming up on VHDL. It's interesting. Two things I can't figure out, and since in both cases it's Quartus (not Modelsim) that's objecting, I thought i would ask here....
Altera_Forum's avatar
Altera_Forum
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14 years ago

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now if I could find an easy way to do 'ifdef and/or `include - any suggestions?

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First, what are you trying to conditionally include?

Generate statements are one option. Configurations are another.

http://www.alteraforum.com/forum/showthread.php?t=30414&page=2

It depends on the context of what you are trying to change.

Could you provide a little more detail.

Cheers,

Dave