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Altera_Forum's avatar
Altera_Forum
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14 years ago

Experienced Verilog coder has 2 Quartus-related VHDL questions..

Hi - after years of Verilog I'm coming up on VHDL. It's interesting. Two things I can't figure out, and since in both cases it's Quartus (not Modelsim) that's objecting, I thought i would ask here....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Sorry - let me explain - I use ifdef primarily to include/exclude code blocks. the generate does that nicely.

"creating packages and declaring appropriate library/use statements" - this sounds complicated - I'll look into it. But my typical problem isn't a log2 function. It's a big table that I auto-generate as VHDL using a Perl script - so it's only used one place. Sounds like i need to extend the Perl to generate the complete entity/architecture .vhd file (up to now it generated only the key part, which I had hoped to 'include').

thanks

/j