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Altera_Forum
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14 years ago

Experienced Verilog coder has 2 Quartus-related VHDL questions..

Hi - after years of Verilog I'm coming up on VHDL. It's interesting. Two things I can't figure out, and since in both cases it's Quartus (not Modelsim) that's objecting, I thought i would ask here....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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Using constant definitions in 'if' and 'case' statements, as FvM says is fine, I would not call it exactly a 'misuse'.

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It's fine in so far, that Quartus has no problem to synthesize it correctly and completely remove the disabled code. But you usually get a lot of warnings.

Generate in contrast is working perfectly for conditional compilation.