Experienced Verilog coder has 2 Quartus-related VHDL questions..

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now if I could find an easy way to do 'ifdef and/or `include - any suggestions?

(I know about the c pre-processor, and the VHDL generate isn't a bad workaround for ifdef, but `include - any thoughts on that would be really appreciated - web search claims I'm SOL)

thanks, best

/j

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'include' you do by creating packages and declaring appropriate library/use statements. So you don't have to copy/paste that log2 function in every module :)

'ifdef': I wouldn't call the 'generate' a work-around. In VHDL-2008 it is quite powerful, but very unfortunately ModelSim (even 10.0c) doesn't digest that.

Using constant definitions in 'if' and 'case' statements, as FvM says is fine, I would not call it exactly a 'misuse'.