Experienced Verilog coder has 2 Quartus-related VHDL questions..

I reviewed your previous posts and found, that the "case (gen_var)" construct is nothing but setting a constant value depending on a generic. This kind of compile time operations can be most simply handled by an array of constants.

Regarding sensitivity list, there's strictly speaking no event at all because genvar is a constant and process(all) doesn't trigger on it. Sensitivity lists are completely ignored for synthesis, in so far the discussion doesn't actually touch Quartus' behaviour. In a simulation, every process will at least run trough once, because the implicite wait statement is at it's end. So the construct should work anyway.

Unfortunately, VHDL has no preprocessor like Verilog, conditional compilation needs to rely on generate (in concurrent code) and "misused" if or case statements with constant arguments (in sequential code).