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Altera_Forum's avatar
Altera_Forum
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14 years ago

Experienced Verilog coder has 2 Quartus-related VHDL questions..

Hi - after years of Verilog I'm coming up on VHDL. It's interesting. Two things I can't figure out, and since in both cases it's Quartus (not Modelsim) that's objecting, I thought i would ask here....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

now if I could find an easy way to do 'ifdef and/or `include - any suggestions?

(I know about the c pre-processor, and the VHDL generate isn't a bad workaround for ifdef, but `include - any thoughts on that would be really appreciated - web search claims I'm SOL)

thanks, best

/j