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Altera_Forum's avatar
Altera_Forum
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14 years ago

Experienced Verilog coder has 2 Quartus-related VHDL questions..

Hi - after years of Verilog I'm coming up on VHDL. It's interesting. Two things I can't figure out, and since in both cases it's Quartus (not Modelsim) that's objecting, I thought i would ask here....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Ie, consider Dave's suggestion

architecture arch of foo is

function my_func(x : integer) return std_logic_vector is

begin

case x is

when 0 => return b"0010";

when 1 => return b"0101";

when others => return b"0101";

end case;

end my_func;

signal val : std_logic_vector ( 3 downto 0 );

begin

val <= my_func(gen_var);

end arch;