Experienced Verilog coder has 2 Quartus-related VHDL questions..

Thanks rbugalho - but I had tried that - turns out an unconstrained wait (i.e., no wait until,etc), makes Quartus very unhappy.

I'm willing to do a different approach. basically the module takes a number 0-31 as a parameter, and in that module I have to translate that into a 32b std_logic_vector of pre-determined value (which is used as a mask). If there's a more 'VHDL' way to do this, lay it on me! 8-}

/j