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Altera_Forum's avatar
Altera_Forum
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14 years ago

Experienced Verilog coder has 2 Quartus-related VHDL questions..

Hi - after years of Verilog I'm coming up on VHDL. It's interesting. Two things I can't figure out, and since in both cases it's Quartus (not Modelsim) that's objecting, I thought i would ask here....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

uhm, uhm

Then, instead of process(all), try to use process without a sensitivy list and simply put a "wait" statement in the end of the process.

process

begin

case (gen_var) is

...

end case;

wait;

end process;

That said, I get the feeling there's a whole different and better aproach to what you need to do... :D