Experienced Verilog coder has 2 Quartus-related VHDL questions..

Ok - the solution (process(all) to question 1 causes the simulator to go to lala land.

The code is

entity foo is

generic (

gen_var : integer;

);

port (

...

);

end entity

architecture arch of foo is

signal val : std_logic_vector ( 3 downto 0 );

process(all)

begin

case (gen_var) is

when

0 => val <= B"0010";

when

1 => val <= B"0101";

...

when

others => val <= B"0110";

end case;

end process;

end;

If I use process(rst_l) --rst_l is another input to the module

it's fine, but process(all) tanks.

thoughts?

thanks!

/j