Experienced Verilog coder has 2 Quartus-related VHDL questions..

1) Use process(all) or use a "when" assignment

2) Still ugly. You're simply not allowed to read from an 'output' in VHDL.

If you need to read back the value of a module's output, you need to use an internal signal instead and then assign that internal signal to the output.

Example:

library ieee;

use ieee.std_logic_1164.all;

entity vhdl_tm is

port (

clk : in std_logic;

x : in std_logic;

y : out std_logic

);

end vhdl_tm;

architecture rtl of vhdl_tm is

signal y_internal : std_logic;

begin

process(clk) begin

if rising_edge(clk) then

if x = '1' then

y_internal <= '0';

else

y_internal <= not y_internal;

end if;

end if;

end process;

y <= y_internal;

end;