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Hi - after years of Verilog I'm coming up on VHDL.
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Good to hear you have seen the light :)
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1) I have a process where a signal is assigned a value using a big case statement based on a generic integer (it's basically a hard-coded lookup table). So there's really no sensitivity list (as the 'sensitive' variable is the generic integer), but also nothing to "wait" on. How do I code this? (right now I created a one-entry sensitivity list using my global reset - but that's a hack).
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Post some code. Perhaps use a function that returns a std_logic_vector?
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2) Quartus has a problem with me using a signal as a primary output. It wants me to use one signal in my code, and then 'assign' it to an output. It complains about the object not being a buffer? I found some -old- posts on this - but what's the right way to do this in 2012?
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Post some code. Its not quite clear what you mean.
Cheers,
Dave
Honored Contributor
