executable file

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'executable' is similar as '.exe' file for C compiler. It allows others to run and test its functionality, but they cannot see the C code inside.

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The analogy for an FPGA is the programming file or .sof file for the FPGA.

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I have no idea if there is a similar '.exe' file for Quartus, so I can let others to test it, but nobody could see the exact code and schematic inside. By the way, my project is implemented in schematic(basic gates). Thanks.

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There's two things you can do; provide the output netlist in Verilog or VHDL format (.vo or .vho file) to allow people to simulate the design, and provide the .sof file. However, the .sof file is specific to a particular FPGA or board.

There must be a way to encrypt designs too. I have never needed to use that, so cannot help. Personally, I prefer to let people see the source code.

Cheers,

Dave