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Altera_Forum
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13 years ago

exclude module from timing synthesis

Hi all!, I want to exclude one module from the timing synthesis so that the good wires are reserved for the rest of the program, which is more timing critical. The specific module is instanti...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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Can I get rid of this warning with a false path declaration?

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You can suppress the message regarding signals being detected as a clock, but without a clock constraint. I had a similar warning from a toggle synchronizer. Here's the thread (along with code and SDC files).

http://www.alteraforum.com/forum/showthread.php?t=34767

Cheers,

Dave