exclude module from timing synthesis

Thanks!

Even after setting these false paths, I get several warnings that a wire in this module "was determined to be a clock but was found without an associated clock assignment".

Indeed, the outputs of this module are connected to the clock input of Flip-Flops to monitor the output of this asynchronous module. Also this module does not use registers.

Does this warning indicate that Quartus still tries to put timing constraints on this module? Can I get rid of this warning with a false path declaration?