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Thanks for your answer.
I think in my case it makes sense to exclude one module, because this module is a research-style asynchronous module with delay lines, where I don't care about the timing (its timing is messed up anyway, because Quartus cannot handle these kinds of designs).
Is there a way to exclude all logic from one module from the timing synthesis?
I believe that the way I proposed in my first message does not work.
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If your module is asynchronous and does not drive next modules and let me assume it does not have clocked registers then TimeQuest will not find any reg-to-reg path to worry about. If it has clocked registers then it has to meet timing at those paths between registers. Thus it may already be excluded by its nature. If it is driving next module then those paths across module from its input to its output may become a very long path hard to meet timing. In that case your design will fail and you shouldn't exclude them.
Anyway, my understanding of set false path is that if applied to registers then it is applied to the path in between two registers and not all the way through. I might be wrong but if true you will need to specify false path from inputs of module to outputs of module.
If your design is for research purpose then when not generate it separately using generate statement or set its clock to zero or fix its inputs to a constant. That way it should be picked up by compiler as null.
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