exclude module from timing synthesis

Thanks for your answer.

I think in my case it makes sense to exclude one module, because this module is a research-style asynchronous module with delay lines, where I don't care about the timing (its timing is messed up anyway, because Quartus cannot handle these kinds of designs).

Is there a way to exclude all logic from one module from the timing synthesis?

I believe that the way I proposed in my first message does not work.