Example design producing errors

I've ran into this error before. If my memory serves me, the reset_kind is set by the VHDL in the dspba_library folder.

If the reset_kind is missing, then try copying the VHDL files from ALTERA_ROOT/17.0/base/quartus/dspba/Libraries/vhdl/base/ into the lib1/dspba_library folder and recompiling the aoclib and aocx binary. More specifically, the dspba_library.vhd and dspba_library_package.vhd files are replaced (might want to open the files to check that they have the reset_kind generic string in there as well)

If that doesn't work, you can try removing the dspba_library requirements in the XML. I haven't found any use for this when making HDL modules for OpenCL so far but I have kept them in when I was running the library examples.

Edit: I should also probably note that these VHDL files are created via DSP Builder which is probably why it is referencing the dspba_library files, although creating custom logic in DSP Builder seems to work fine for me without this folder when integrating into OpenCL.