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Altera_Forum
Honored Contributor
Honored Contributorestimate total pipeline latency for kernel
Hi, I'm new to using Intel's OpenCL SDK for FPGAs . I'm developing a single work-item kernel and I'm experimenting with code changes and would like to see the effect of these changes on my to...
Altera_ForumHonored Contributor
Honored Contributor@HRZ really appreciate your quick response !
I was kind of hoping there was a way to extract this from the offlince compiler / generated files/quartus project as this gets tricky for complex designs with stalls (as you said) :(
