Errors with parametrized instantiation of custom componenten in platform designer

Hi,

I am trying to implement a custom component consisting of a .VHD and a HW.TCL file. My target is to dynamically modify the width of an input port when a parameter of the component changes. The application is pretty simple: The parameter g_desc_size specifies the size of an array in the component and g_adr_width is calculated depending on that value.

The port definitions in VHDL look like this:

  generic (
    g_desc_size               : integer := 256                              ;
    g_adr_width               : integer := 8                                ;
    ..
  );
  port (
    ..
    asi_data_channel_i        :  in std_logic_vector(g_adr_width-1 downto 0);
    ..
  );

The paramter definition in the TCL file look mlike this:

add_parameter g_desc_size integer
set_parameter_property g_desc_size DEFAULT_VALUE 256
set_parameter_property g_desc_size ALLOWED_RANGES 2:256
set_parameter_property g_desc_size AFFECTS_ELABORATION true
set_parameter_property g_desc_size AFFECTS_GENERATION true

add_parameter g_adr_width integer
set_parameter_property g_adr_width DEFAULT_VALUE 8
set_parameter_property g_adr_width ALLOWED_RANGES 1:8
set_parameter_property g_adr_width DERIVED true
set_parameter_property g_adr_width ENABLED false
set_parameter_property g_adr_width AFFECTS_ELABORATION true
set_parameter_property g_adr_width AFFECTS_GENERATION true

I have also added a elaboration callback function, for the calculation of g_adr_width, that looks like this:

proc elaboration_callback {} {
  set_parameter_value g_adr_width [ expr ceil(log([get_parameter_value g_desc_size])/log(2)) ]
  set_port_property asi_data_channel_i WIDTH_EXPR [ get_parameter_value g_adr_width ]
}

The elaboration callback is enabled with set_module_property ELABORATION_CALLBACK elaboration_callback

Now when I try to compile the design with the parameter g_desc_size set to 4 in Platform Designer (so 2 is the correct value for the port width) an error messages comes up that says:

Error (12005): Actual width (2) of port "asi_data_channel_i" on instance "<instance_name>" is not compatible with the formal port width (8) declared by the instantiated entity

When I try to compile the design without a default value for g_adr_width in the VHD file, Quartus tells me that the generic needs a default or actual value.

Within the Platform Designer there doesn't seem to be a problem; the port width of the above mentioned signal changes as intended and there are no problems when generating the HDL code.

I have looked through the files that were generated with the Generate HDL in Platform Designer and I don't really see a problem: The component decleration in the PKG.VHD file has the correct port width of 2.

What is the solution to this? I am sure that it'll be pretty obious for someone that has already worked with custom components, but this is my first time implementing one.
Do I need to add a generation callback function too?

Best Regards,
Florian