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Honored Contributor
Honored ContributorErrors when trying to create 24 hr clock in Quartus II using VHDL
I am news to VHDL and trying to create a 24 hr clock with hours, minutes and seconds that outputs on the seven segment display but I am getting errors and have been unable to resolve them. Here is th...
Altera_ForumHonored Contributor
Honored ContributorYour "ring" components only has std_logic_vector ports, but you are trying to connect a single bit clock to a 4 bit vector.
Did you mean to have the clock2 signal as a std_logic_vector?
