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Altera_Forum
Honored Contributor
9 years agoYour "ring" components only has std_logic_vector ports, but you are trying to connect a single bit clock to a 4 bit vector.
Did you mean to have the clock2 signal as a std_logic_vector?Your "ring" components only has std_logic_vector ports, but you are trying to connect a single bit clock to a 4 bit vector.
Did you mean to have the clock2 signal as a std_logic_vector?