error

library ieee;

use ieee.std_logic_1164.all;

entity uppgift4a_synkron is

port (

-- Insignaler

CLOCK, reset_n : IN std_logic;

KEY_0, KEY_1 : IN std_logic;

-- Utsignaler

LEDG_0, LEDG_1 : OUT std_logic);

end entity;

architecture rtl of uppgift4a_synkron is

-- Build an enumerated type for the state machine

type state_type is (oppen,stangd);

-- Register to hold the current state

signal state : state_type;

begin

process (reset_n, CLOCK)

begin

if reset_n = '0' then

state <= oppen;

LEDG_0 <= '0';

LEDG_1 <= '0';

elsif rising_edge(CLOCK) then

case state is

when oppen => if KEY_0 ='1' then

end if;

end process;

begin

case state is

when oppen=> if KEY_0='1' then

LEDG_0 <='0';

else

LEDG_0 <='1';

end if;

LEDG_1 <='0';

when stangd=>if KEY_1='1'then

LEDG_0 <='1';

elsif

LEDG_0= '0' then

LEDG_0 <='0';

else

LEDG_0 <='1';

end if;

LEDG_1 <='1';

end case;

end process;

end;

Here is the rest im so sorry

oppen=open and

stangd=closed