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The version of modelsim that ships with Quartus 15 is able to do mixed language.
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Hmm, I guess I don't have that license then. I do have a license for Quartus II Standard Edition though, and just reaffirming, that doesn't help me at all?
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The Licence you have is the free one that comes with modelsim altera edition and is not able to simulate mixed language designs.
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The two IP cores that appear to no have a verilog option are LPM Counter and ROM 1-Port. Are there alternative IP cores that have a verilog option, or can I simply not sure those?
EDIT: Recreating the cores (they were originally created I think in QII v12 as verilog seems to have allowed me to output verilog black box files. I'll give those a go.
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