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Altera_Forum
Honored Contributor
Honored ContributorError while executing: Force
Hello all, I recently installed ModelSim, and am having all sorts of issues with it. I am trying to simulate a project that contains several Altera IP cores (counter, ROM, PLL, ALTDIDO) and am ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Im guessing you dont have a dual language capability in your licence. The cheaper versions of modelsim only have single language capabilities. --- Quote End --- Is there an easy way to verify that this is the cause? Can I 'view' the license for ModelSim? If I did all of my work in Verilog, does that mean the IP cores (if this is the issue) are all, by default, VHDL? Is there a way to convert them to verilog?
