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Altera_Forum's avatar
Altera_Forum
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10 years ago

Error while executing: Force

Hello all, I recently installed ModelSim, and am having all sorts of issues with it. I am trying to simulate a project that contains several Altera IP cores (counter, ROM, PLL, ALTDIDO) and am ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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Im guessing you dont have a dual language capability in your licence. The cheaper versions of modelsim only have single language capabilities.

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Is there an easy way to verify that this is the cause? Can I 'view' the license for ModelSim? If I did all of my work in Verilog, does that mean the IP cores (if this is the issue) are all, by default, VHDL? Is there a way to convert them to verilog?