Contributorerror when open IP from the platform designer
Dear Support/Expert,
While I am open a ip, which I know it is good and compiled successfully, but when I open it from the platform designer, I will have this error.
Info: Reading index C:\intelfpga_pro\21.3\qsys\lib\root_components.ipx
Info: C:\intelfpga_pro\21.3\qsys\lib\root_components.ipx: Loading now from components.ipx
Info: Reading index C:\intelfpga_pro\21.3\qsys\lib\ip_component_categories.ipx
Info: C:\intelfpga_pro\21.3\qsys\lib\ip_component_categories.ipx described 0 plugins, 0 paths, in 0.01 seconds
Info: C:/intelfpga_pro/21.3/qsys/lib/ip_component_categories.ipx matched 1 files in 0.02 seconds
Info: C:/FPGA/TSW14J57_pro/HiLo_XCVR_16lane_pro/ip/ip/jesd204b/ip/**/* matched 0 files in 0.00 seconds
Info: C:/FPGA/TSW14J57_pro/HiLo_XCVR_16lane_pro/ip/ip/jesd204b/* matched 63 files in 0.14 seconds
Info: Reading index C:\FPGA\TSW14J57_pro\HiLo_XCVR_16lane_pro\ip\ip\jesd204b\jesd204b_emif_0_tb\jesd204b_emif_0.ipx
Info: C:\FPGA\TSW14J57_pro\HiLo_XCVR_16lane_pro\ip\ip\jesd204b\jesd204b_emif_0_tb\jesd204b_emif_0.ipx described 0 plugins, 3 paths, in 0.00 seconds
Info: C:/FPGA/TSW14J57_pro/HiLo_XCVR_16lane_pro/ip/ip/jesd204b/*/* matched 442 files in 0.07 seconds
Info: C:/FPGA/TSW14J57_pro/HiLo_XCVR_16lane_pro/prj/* matched 17 files in 0.00 seconds
Info: C:/intelfpga_pro/21.3/qsys/lib/$$QUARTUS_IP_USERDIR/* matched 0 files in 0.00 seconds
Info: C:/intelfpga_pro/21.3/qsys/lib/$$QUARTUS_IP_GLOBALDIR/* matched 0 files in 0.00 seconds
Info: Reading index C:\intelfpga_pro\21.3\ip\altera\altera_components.ipx
Info: Reading index C:/intelfpga_pro/21.3/ip/altera/hw_altera_components.iipx
Info: C:/intelfpga_pro/21.3/ip/altera/hw_altera_components.iipx described 3022 plugins, 0 paths, in 0.31 seconds
Info: Reading index C:/intelfpga_pro/21.3/ip/altera/sw_altera_components.iipx
Info: C:/intelfpga_pro/21.3/ip/altera/sw_altera_components.iipx described 80 plugins, 0 paths, in 0.01 seconds
Info: C:\intelfpga_pro\21.3\ip\altera\altera_components.ipx described 0 plugins, 2 paths, in 0.32 seconds
Info: Reading index C:\intelfpga_pro\21.3\ip\altera\toolkits.ipx
Info: C:\intelfpga_pro\21.3\ip\altera\toolkits.ipx described 28 plugins, 0 paths, in 0.01 seconds
Info: C:/intelfpga_pro/21.3/ip/**/* matched 131 files in 0.34 seconds
Info: C:/intelfpga_pro/ip/**/* matched 0 files in 0.00 seconds
Info: Reading index C:\intelfpga_pro\21.3\qsys\lib\builtin.ipx
Info: C:\intelfpga_pro\21.3\qsys\lib\builtin.ipx described 95 plugins, 0 paths, in 0.01 seconds
Info: C:/intelfpga_pro/21.3/qsys/lib/builtin.ipx matched 1 files in 0.01 seconds
Info: C:/intelfpga_pro/21.3/quartus/common/librarian/factories/**/* matched 0 files in 0.00 seconds
Info: C:/intelfpga_pro/21.3/qsys/lib/$IP_IPX_PATH matched 1 files in 0.00 seconds
Info: C:\intelfpga_pro\21.3\qsys\lib\root_components.ipx described 0 plugins, 12 paths, in 0.58 seconds
Info: C:/intelfpga_pro/21.3/qsys/lib/root_components.ipx matched 1 files in 0.58 seconds
Error: Failed to retrieve source file from Quartus project, manually re-run the following commands in Quartus tcl shell.
Error: set filesList [list]; foreach_in_collection file [get_all_assignments -type global -name IP_FILE] { append filesList [get_assignment_info $file -value]\; }; return $filesList;
I don't understand what the last line means.
thanks.
David
