Honored Contributorwe have problem in compiling VHDL code in Quartus II software. Every time we compile it shows the Error:top level design entity " file name" is undefined.
We are even taking care of the case sensitivity. Our file name, new created project name and entity name in the code are all same. Plz help us regarding this.
New ContributorHello,
"Error: Top-level design entity "*NAME*" is undefined"
This is what I did to correct.
1) check paths for spaces, none allowed.
2) check entity name can not start with number.
3) Assignment - Settings - General - Top-Level Entity - "..."
4) From bottom up. select next entity up. Apply - OK.
5) Processing - "Start Compilation"
6) When complete. Tools - "Netlist Viewers" - "RTL Viewer"
Don't know if this step is necessary. It's what I did.
7) Repeat from step 3) moving up for each entity in list.
"Entity Name"
9) Done
This created what was missing that was needed.
I worked for me hope it works for you.
