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Altera_Forum's avatar
Altera_Forum
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17 years ago

error regarding register inference

Hi,

I have declared an integer type signal named q in the architecture declaration region.

I m getting an error, which i could not comprehend...

can't infer register for "q[18]" because its behavior does not match any supported register model

the same error is displayed for q[0] to q[18]

plz help me out...

Thanks...

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Could you post the relevant VHDL code fragment for forum members to take a look at please?

    It sounds more to do with what you are doing with the q signal rather than how you have declared it