Compile optimization crashes like this cannot be fixed by the user, you have to directly open a service request with Altera for that. What you should expect is that they will probably tell you this code is too complex for the specific architecture of an FPGA and you would have to rewrite it in a way that it better matches the underlying FPGA architecture. What I can tell you is that even if the code compiles without issues, it will perform terribly because an FPGA's architecture is completely different from a GPU; you will eventually have to rewrite it if you want to get proper performance.
P.S. You should probably try compiling the code using the latest Quartus v16.1.2 and against one of Altera's reference BSPs first before reporting; they might have already fixed the issue in the latest version.