This error happens coz the IP's referenced in the design are outdated v10/11 and needs to be updated. To get around this you will have to manually upgrade and regenerate all of the philosopher systems.
- Load the entire design (top-level Qsys file and other Qsys subsystem files) along with the rest of the HDL modules into Quartus.
- In the Project Navigator Pane, select Files or IP Units . This will now show the 4 Philosopher subsystems along with the main system.
- Double-click a single subsystem to open it. This will force Qsys to regenerate the IPs in the design and upgrade them.
- When the design is open, select the CPU in each subsystem and open its Properties in the right pane.
- Here select the NIOS-2/e CPU instead of NIOS-2/f.
- Click Finish button, and then Save the subsystem.
- Generate the subsystem and close it.
- Perform the same for the rest of the subsystems as well as for the main CPU.
- Change the CPU to NIOS-2/e and regenerate.
- You will also have to comment out the fsa and fsd ports in the top-level.v HDL file.
- You will also have to re-assign the pins to the correct values on the MAX10 FPGA board. You can remove all other Pin assignments and keep only the ones used in the top-level file.
- Save the file and then Compile the whole design.
This should get it working.
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