Error loading design in Modelsim Altera

Hi all,

I'm trying to build a verification environment that look like the block diagram below.

Where client send instruction to server, then server drive the signals that interface to the dut.

Verifier is the data verification when the test is finish and task is data structure to store data.

See attached for verilog code for the bfm_top

By setting academic_x86_subcore as TOP-LEVEL ENTITY, and BFM_TOP as my testbench file to compile.

I get successful compilation. But when I trying to run RTL simulation. Modelsim Altera show Error Loading Design, I couldn't figure out what is the problem. I did some experiment and it seem testbench not able to instantiate more than 1 module, it flag error loading design when running RTL simulation

See attached for log I got from Modelsim Altera

Thanks!

Jason