Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Error in gate-level timing simulation using modelsim

When the design is synthesized and the FPGA target is either CYCLONE or CYCLONEII, the gate-level timing simulation operates properly. But, when the same design is synthesized and the target FPGA is ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I synthesized the design at three different FPGAs(CYCLONE,CYCLONEII,CYCLONEIII), and i used the same testbench for the three cases. On Modelsim, in case of CYCLONE, pre-compiled simulation library of CYCLONE was required, in case of CYCLONEII, pre-compiled simulation library of CYCLONEII was required, and in case of CYCLONEIII, two pre-compiled simulation libraries were required (CYCLONEIII,ALTERA). For each case, i used the .vho and .sdo file of it. The results of the simulation are as expected in case of CYCLONE and CYCLONEII, but in case of CYCLONEIII it wasn't true. The timing analysis report has no timing violations. Is there extra configuration for ModelSim in case of CYCLONEIII ?