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Altera_Forum
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13 years ago

Error in gate-level timing simulation using modelsim

When the design is synthesized and the FPGA target is either CYCLONE or CYCLONEII, the gate-level timing simulation operates properly. But, when the same design is synthesized and the target FPGA is ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I'm sure that the testbench set up the to meet the timing requirements.

If the timing requirements aren't met, the simulation should fail at any target FPGA, but it succeeded when the target FPGA is CYCLONE or CYCLONEII and fails when the target FPGA is CYCLONEIII.