Error in gate-level timing simulation using modelsim

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When the design is synthesized and the FPGA target is either CYCLONE or CYCLONEII, the gate-level timing simulation operates properly. But, when the same design is synthesized and the target FPGA is CYCLONEIII, the gate-level timing simulation doesn't work properly.

Is there a reason for this ?

Thanks :)

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The testbench does not set up the inputs to meet the timing requirements.

Kevin Jennings