Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Error in case staement

I am trying to run a small code of VHDL on Quartus and it errors out saying error (10321): VHDL error at PPC_PCI_SM.vhd(499): choice ""10H"" overlaps with a previous choic error (10321): VHDL er...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

It's legal VHDL but questionable for synthesis. You can use '1', '0', 'Z', and sometimes 'X' (but only on the right-hand side of an assignment) but I'd avoid H and L altogether. These are meta-values that don't have any utility for a digital logic synthesis tool. They typically bit-encoded std_ulogic, so you only get 1/0 and hence the aliasing you're seeing.