Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorError in altera modelsim
Hello guys, i have a problem with simulation in altera modelsim about serial input parallel output shifter register vhdl code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD....
Altera_ForumHonored Contributor
Honored ContributorYou declare the entity port D as unsigned but in the component declaration it is a std_logic_vector
