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Honored Contributor
Honored ContributorError in altera modelsim
Hello guys, i have a problem with simulation in altera modelsim about serial input parallel output shifter register vhdl code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD....
Altera_ForumHonored Contributor
Honored ContributorD is unsigned and you declared as std_logic_vector?
