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Altera_Forum
Honored Contributor
Honored ContributorError in altera modelsim
Hello guys, i have a problem with simulation in altera modelsim about serial input parallel output shifter register vhdl code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD....
Altera_ForumHonored Contributor
Honored ContributorWhen instaining component use always named association for formal and real parameters. try avoid association by position or better forget forever.
when declaring component just simply copy entity defintion and proper replace 'entity' keyword with 'component' according to VHDL syntax.
