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Honored Contributor
Honored ContributorError in altera modelsim
Hello guys, i have a problem with simulation in altera modelsim about serial input parallel output shifter register vhdl code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD....
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Failure: (vsim-3807) Types do not match between component and entity for port "D". --- Quote End --- you have difference in entity and component declaration -> please check. You can use different order of ports while instaining component but do not do this in component declaration. meanwhile you testbench cover only 'reset' signal and make meanigful comments. you have process with signal 'clk' but comment as 'execute only once'.
