New ContributorError: can't read "FileWatch(fileName)": no such element in array
Determining the location of the ModelSim executable...
Using: C:\intelFPGA_lite\20.1\modelsim_ase\win32aloem
To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
**** Generating the ModelSim Testbench ****
quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off mux_2_1 -c mux_2_1 --vector_source="D:/report/Waveform.vwf" --testbench_file="D:/report/simulation/qsim/Waveform.vwf.vt"
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
Info: Copyright (C) 2020 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Fri Sep 25 23:39:49 2020
Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off mux_2_1 -c mux_2_1 --vector_source=D:/report/Waveform.vwf --testbench_file=D:/report/simulation/qsim/Waveform.vwf.vt
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Completed successfully.
Completed successfully.
**** Generating the timing simulation netlist ****
quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="D:/report/simulation/qsim/" mux_2_1 -c mux_2_1
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
Info: Copyright (C) 2020 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Fri Sep 25 23:39:50 2020
Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory=D:/report/simulation/qsim/ mux_2_1 -c mux_2_1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Warning (10905): Generated the EDA functional simulation netlist because it is the only supported netlist type for this device.
Info (204019): Generated file mux_2_1.vo in folder "D:/report/simulation/qsim//" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings
Info: Peak virtual memory: 4742 megabytes
Info: Processing ended: Fri Sep 25 23:39:51 2020
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Completed successfully.
**** Generating the ModelSim .do script ****
D:/report/simulation/qsim/mux_2_1.do generated.
Completed successfully.
**** Running the ModelSim simulation ****
C:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/vsim -c -do mux_2_1.do
Reading pref.tcl
# 2020.1
# do mux_2_1.do
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 23:39:52 on Sep 25,2020
# vlog -work work mux_2_1.vo
# -- Compiling module mux_2_1
#
# Top level modules:
# mux_2_1
# End time: 23:39:52 on Sep 25,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 23:39:52 on Sep 25,2020
# vlog -work work Waveform.vwf.vt
# -- Compiling module mux_2_1_vlg_vec_tst
#
# Top level modules:
# mux_2_1_vlg_vec_tst
# End time: 23:39:52 on Sep 25,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Error loading design
Error loading design
Error: can't read "FileWatch(fileName)": no such element in array
Error.
