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Altera_Forum
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8 years ago

Error 332000 when using DCFIFOs in Qsys during build

I received this error message in Quartus Prime Lite 16.1 when attempting to add a dual-clock FIFO to Qsys on a DE2i-150 example project. I tested this with the DE2i-150 PCI-E Fundamental example proj...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi DJ,

I am getting the same compile error for a different PCIe related DE2i-150 design in Quartus 17.0. Did you ever find a resolution to this? In your case did you try just deleting system_sample_fifo.sdc ?

Regards,

Aidan