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JJLiu's avatar
JJLiu
Icon for New Contributor rankNew Contributor
3 years ago

Error (293007): Current module quartus_map ended unexpectedly.

Hi, I had trouble compiling a simple module : Error (293007): Current module quartus_map ended unexpectedly. Verify that you have sufficient memory available to compile your design. You can vie...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Quartus tool does support +: and -: part-selects.

Reference:

https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#hdl/vlog/vlog_list_support_d1625e286.htm

Instead, I saw these errors when try to run fitter stage. You may need to check your design.

Error(22412): The design requires at least 16419 elements of type IO_CLUSTER but the device has only 1857.

Error(22412): The design requires at least 16393 elements of type IO_OUTPUT_BUFFER but the device has only 1037.

Error(22412): The design requires at least 16419 elements of type IO_PAD but the device has only 1269.

Error(16297): An error has occurred while trying to initialize the plan stage.

Best Regards,

Richard Tan

JJLiu's avatar
JJLiu
Icon for New Contributor rankNew Contributor
3 years ago

Thank you for your attention to my question!
I used virtual pins to avoid the errors you pointed out.


But it still doesn't explain why code with "+ : "compiles out of memory, while code with the same functionality compiles quickly with no errors.
Sometimes it is unavoidable to use "+ :" and "- :" for dynamic interception of fixed bit width. That's when I hit a standstill...So should I set up Quartus to support "+ :"?


In fact, I have selected the Verilog version as Verilog-2001:

I would be grateful if you could give me your advice！