Error (293007): Current module quartus_map ended unexpectedly.

Thanks for your reply!
In fact, "+:" and "- :" are syntax in verilog2001.
"That syntax is called an indexed part-select. The first term is the bit offset and the second term is the width. It allows you to specify a variable for the offset, but the width must be constant."
I tried to change my code to show you what this syntax does, like this:

module convlayerSingle(inputPart,addr,outputWhole);
    input [0:16-1] inputPart; 
    input [9:0] addr;
    output reg [0:1024*16-1] outputWhole; //32*32*16
    integer i;
    always @ (*) begin
        //outputWhole = 0;
        //outputWhole[addr*16 +: 16] = inputPart[0:16-1];
        for(i=0;i<16;i=i+1) begin
            outputWhole[addr*16+i]=inputPart[i];
        end
    end
endmodule

But something unexpected happened: Quartus finished compiling the changed code in a very short time, and there were no errors!
Well, maybe Quartus doesn't support this weird syntax?
Thanks again for your reply, it was you who helped me solve this problem!