Error (18496): The Output SCLK in pin 26 is too close to PLL clock input in pin 27

We have comae against this problem as well. We have an existing board design on which we are adding additional FPGA functionality that uses the two pins either side of the PLL clock input, pin 27 on an 10M04SCE144C8G device. We get errors like:

"Error (18496): The Output wifi_enable in pin location 28 (pad_828) is too close to PLL clock input pin (clk_24) in pin location 27 (pad_12)"

In our case these signals are rarely toggled, mainly just at power up, so we believe these shouldn't cause any issues.

We have tried adding:

"set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to wifi_enable" to the projects *.qsf file, as mentioned above, however this has no effect, the errors are still reported. We are using Quartus18.1.0 Build 625 09/12/2018 SJ Lite Edition.

Doesn't the IO_MAXIMUM_TOGGLE_RATE setting work any more or could there be another reason why this does not mask the error ?

Terry