Error (18496): The Output SCLK in pin 26 is too close to PLL clock input in pin 27

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stmilos,

I don't want to sound like your mother, but this demonstrates why you should ALWAYS create a top level design in Quartus and do pin assignments BEFORE committing to hardware.

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One does not always completely finish the internal logic before the physical hardware, and I find these very specific restrictions horribly obscure and unexpected.

I'm having the exact same problem on a 10M02. I use a clock control block to switch between three clocks (the input clock and two output clocks of a single PLL), and it is accepted fine on its own, but when I try to use a second clock control block with the exact same inputs (just a different output) suddenly this error 18496 occurs. And a toggle rate of 0 MHz on the pin that is deemed 'too close' does not seem to help.