Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Error 17044 in nios design with sdram

Hi, I have built a design using Nios core and sdram (dd3 sdram controller with UniPHY). I get the following error during compilation: Error (17044): Illegal connection found on I/O input b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I dont think I have connected it wrongly. What are the correct connections to make? I just have two connections, the clock and reset. What connections are to be made for the sdram?