Forum Discussion
Hello there ,
Looks like 3.3 V LVTTL / LVCMOS support the OCT with and without calibration, Refer table 6.3 in cyclone III handbook .
In Cyclone III ,there are only 4 calibration blocks. Each block paired between two banks. For example there is one OCT calibration block in bank 2 which is common for bank 1. Can you please check OCT applied right calibration banks which you have RPU/RDN connected ?
Also note from handbook there are " two I/O banks sharing the same calibration block, both banks must have the same VCCIO if both banks enable OCT calibration ".Can you make sure VCCIO is same?
Can you also check PCI diode is enabled in the same OCT applied pins ?
Here is link for OCT IP user guide for your reference,
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_oct.pdf
In additional to this , there is one more way you can reduce the overshoot is by changing the source drive current :) .
Thank you