Forum Discussion
Altera_Forum
Honored Contributor
10 years agoError (10822)
Hello, please help me with this problem. Code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity encoder is port( clk:in std_logic; A:in...
Altera_Forum
Honored Contributor
10 years ago --- Quote Start --- Although being a bad style, is it supposed to be an error at all ? Just a guess, but would't be due to the fact that the code has cascaded "if...end if" implementations for the same variable ?
...
if B='0' then
number<=number + 1;
end if;
if B='1' then
number<=number - 1 ;
... --- Quote End --- The error in the in the post titles - it appears the OP is trying to synthesise the design - which for and FPGA would be illegal with 2 edges.